Publication List

  • Journal Papers

    • [1] Yu-Guang Chen, Wan-Yu Wen, Yiyu Shi, Wing-Kai Hon, and Shih-Chieh Chang, “Novel Spare TSV Deployment for 3D ICs Considering Yield and Timing Constraints,” in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Volume:34, Issue: 4, pp.577-588, April 2015 [SCI, EI]

    • [2] Yu-Guang Chen, Hui Geng, Kuan-Yu Lai, Yiyu Shi, and Shih-Chieh Chang, “Multi-Bit Retention Registers for Power Gated Designs: Concept, Design and Deployment,” in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Volume:33, Issue: 4, pp. 507-518, April 2014 [SCI, EI]

  • Conference Papers

    • [1] Kun-Wei Chiu, Yu-Guang Chen, and Ing-Chao Lin, “An Efficient NBTI-Aware Wake-Up Strategy for Power-Gated Designs,” in Proc. of Design, Automation & Test Conference in Europe (DATE), pp. 901-904. Dresden, Germany, March 2018. (Acceptance rate: 24%)

    • [2] Yu-Guang Chen, Michihiro Shintani, Takashi Sato, Yiyu Shi, and Shih-Chieh Chang, “Pattern Based Runtime Voltage Emergency Prediction: An Instruction-Aware Block Sparse Compressed Sensing Approach,” in Proc. of Asia and South Pacific Design Automation Conference (ASP-DAC), pp.543-548, Chiba/Tokyo, Japan, Jan. 2017 (Invited paper)

    • [3] Yu-Guang Chen, Wan-Yu Wen, Yun-Ting Wang, You-Luen Lee, and Shih-Chieh Chang, “A Novel Low-Cost Dynamic Logic Reconfigurable Structure Strategy for Low Power Optimization,” in Proc. of Asia and South Pacific Design Automation Conference (ASP-DAC), PP. 250-255, Macau, China, Jan. 2016 (Acceptance rate: 34.3%)

    • [4] Yu-Guang Chen, Wan-Yu Wen, Tao Wang, Yiyu Shi and Shih-Chieh Chang, “Q-Learning Based Dynamic Voltage Scaling for Designs with Graceful Degradation,” in Proc. of International Symposium on Physical Design (ISPD), pp.41-48, Monterey, CA, USA, March 2015 (Best Paper Nomination, 3 out of 44) (Acceptance rate: 37.8%)

    • [5] Yu-Guang Chen, Tao Wang, Kuan-Yu Lai, Wen-Yu Wen, Yiyu Shi, and Shih-Chieh Chang, “Critical Path Monitor Enabled Dynamic Voltage Scaling for Graceful Degradation in Sub-Threshold Designs,” in Proc. of IEEE/ACM Design Automation Conference (DAC), pp.1-6, San Francisco, CA, USA, June 2014 (Acceptance rate: 22.1%)

    • [6] Yu-Guang Chen, Kuan-Yu Lai, Ming-Chao Lee, Yiyu Shi, Wing-Kai Hon, and Shih-Chieh Chang, “Yield and Timing Constrained Spare TSV Assignment for Three-Dimensional Integrated Circuits,” in Proc. of Design, Automation & Test in Europe (DATE), pp.1-4, Dresden, Germany, March 2014 (Acceptance rate: 23.1%)

    • [7] Yu-Guang Chen, Yiyu Shi, Kuan-Yu Lai, Geng Hui, and Shih-Chieh Chang, “Efficient Multiple-Bit Retention Register Assignment for Power Gated Design: Concept and Algorithms,” in Proc. of IEEE/ACM International Conference on Computer-aided Design (ICCAD), pp.309-316, San Jose, CA, USA, Nov. 2012 (Acceptance rate: 24.3%)

    • [8] Ming-Chao Lee, Yiyu Shi, Yu-Guang Chen, Diana Marculescu, and Shih-Chieh Chang, “Efficient On-line Module-level Wake-up Scheduling for High Performance Multi-module Designs,” in Proc. of International Symposium on Physical Design (ISPD), pp.97-104, Napa Valley, CA, USA, March 2012 (Acceptance rate: 33%)

    • [9] Ming-Chao Lee, Yu-Guang Chen, Ding-Kei Huang, and Shih-Chieh Chang, “NBTI-Aware Power Gating Design,” in Proc. of Asia and South Pacific Design Automation Conference (ASP-DAC), pp.609-614, Yokohama, Japan, Jan. 2011 (Acceptance rate: 34.4%)

  • Book Chapters

    • [1] Yu-Guang Chen, Shi-Chieh Chang and Yiyu Shi, “Live Free or Die Hard: Design for Reliability in Three-Dimensional Integrated Circuits,” Chapter 9 in Physical Design for 3D Integrated Circuits, edited by Aida Todri-Sanial and Chuan Seng Tan, pp.193-227, CRC Publishing, Dec. 2015 (ISBN: 978-1498710367)
  • Workshop Papers & Posters

    • [1] Yu-Guang Chen, Kun-Wei Chiu, and Ing-Chao Lin, “A Novel NBTI-Aware Wake-Up Strategy for Power-Gated Designs,” in the 21st Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI), Mastue, Japan, Mar. 2018

    • [2] Kun-Wei Chiu, Yu-Guang Chen, and Ing-Chao Lin, " An Efficient Wake-up Strategy Considering Aging Effect for Power-Gated Designs," in the 28th VLSI Design / CAD Symposium (VLSI/CAD), Pingtung, Taiwan, Aug. 2017.

    • [3] Yu-Guang Chen, Yiyu Shi, and Shih-Chieh Chang, “Novel Spare TSV Deployment for 3D ICs Considering Yield and Timing Constraints,” in SIGDA Student Research Forum at of Asia and South Pacific Design Automation Conference (ASP-DAC), Jan. 2016

    • [4] Yu-Guang Chen, Yiyu Shi, and Shih-Chieh Chang, “Dynamic Voltage Scaling for Designs with Graceful Degradation – Statistic and Learning Based Approaches,” in ACM Student Research Competition at IEEE/ACM International Conference on Computer-aided Design (ICCAD), Nov. 2015

    • [5] Yu-Guang Chen, Yiyu Shi, and Shih-Chieh Chang, “Critical Path Monitor Enabled Dynamic Voltage Scaling for Designs with Graceful Degradation,” in PhD Forum at IEEE/ACM Design Automation Conference (DAC), June 2015

    • [6] Yu-Guang Chen, Yiyu Shi, Kuan-Yu Lai, Ming-Chao Lee, Wing-Kai Hon, and Shih-Chieh Chang, “Yield and Timing Constrained Spare TSV Assignment for Three-Dimensional Integrated Circuits,” in Work-in-Progress session at Design Automation Conference (DAC), June 2013

    • [7] Yu-Guang Chen, Yiyu Shi, Kuan-Yu Lai and Shih-Chieh Chang, “Efficient Retention Register Assignment for Power Gated Designs,” in International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), Jan. 2012

    • [8] Ming-Chao Lee, Yiyu Shi, Yu-Guang Chen, Shih-Chieh Chang, and Diana Marculescu, “Efficient Wake-Up Scheduling for Multi-Core Systems,” in International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), Jan. 2011